Exemplary embodiments relate to a low-power and high-resolution time-to-digital converter, and more particularly, to a low-power and high-resolution time-to-digital converter configured to detect a phase error between a retimed reference clock and a reference clock.
A charge pump PPL (Phase Locked Loop) has been generally used to design RF frequency synthesizer for multiband mobile communication in the related art and analog circuit design technologies are integrated in the charge pump PPL. Accordingly, a specific additional analog/RF library is required, other than an analog circuit and a design library that is provided in a standard digital CMOS process due to analog signal characteristics, so that it is difficult to integrate with a digital baseband signal processing block.
Further, as a nanoscale digital CMOS process has been recently developed, digital baseband signal processing blocks have also been increasingly developed by using the nanoscale digital CMOS process. With the change of development of the nanotechnology, digital circuits can be implemented by being easily adopted t a process technology for desired manufacturing, substantially without redesigning, but there is a problem in that it is necessary to redesign the analogy/RF integrated circuit every time the process technology is changed, and there is a defect in that an operation voltage decreases, as the CMOS process technology is correspondingly developed into the nanoscale.
Therefore, it takes a lot of time and cost to improve various problems in designing the analog/RF integrated circuit in the nanoscale digital CMOS process, so that researches about digital RF that gradually digitalizes the analog/RF circuit have been intensively conducted. In particular, the frequency synthesizer in the RF transceivers is a part that can be completely digitalized. Although the digital PLL frequency synthesizer has a long history, but the phase noise and the jitter characteristics are poor, so that the digital PLL frequency synthesizer has not been substantially used for the local oscillator of RF transceiver for mobile communication that requires high-quality phase noise.
However, a new type of ADPLL (all digital PLL) was developed a few years ago by applying the digital PLL technology to a frequency synthesizer for mobile communication. The difference between the ADPLL and the digital PLL of the related art is the DCO (Digitally Controlled Oscillator), and the past DCO oscillator of the related art is implemented by using a digital logic but the recent DCO oscillator is implemented by using an LC resonator. Therefore, since the DCO is designed by using an LC resonator, the phase noise or the jitter noise is very excellent more than the DCO using the past digital logic.
Since the DCO oscillator using an LC resonator controls the oscillation frequency by controlling a fine amount of change in capacitance of the LC resonator, the capacitor bank is divided into a coarse control bank and a fine control bank. The coarse control bank of the DCO is used to quickly find a PLL lock for a desired PLL frequency and is converted into the fine control bank by a mode conversion signal when the objective PLL frequency is almost reached by the coarse control bank, in which the fine control bank is used and the objective PLL frequency is locked by fine tracking.
The fractional phase error ε that is used for the fine tracking is generated by a time-to-digital converter a fine phase difference between the reference signal and DCO output signal is compensated through an arithmetical operation phase detector by a fractional phase error signal.
In this case, the phase noise performance of the existing digital PLL is determined by the resolution of the fractional phase error ε that the time-to-digital converter can detect. That is, the higher the detected resolution of the fractional phase error ε of the time-to-digital converter, the more the phase noise becomes good, and the phase error detection resolution is determined by the minimum inverter delay time of an inverter chain constituting the time-to-digital converter. However, as disclosed in Korean Patent Publication No. 2010-0130205, the inverter chain of time-to-digital converters that has been invented before has a defect in that power consumption and noise contribution are large, because the inverter chain should operate at a high DCO clock frequency.
The technical field of the present invention is disclosed in a ‘high-speed time-digital converter’ disclosed in Korean Patent Publication No. 10-2010-0130205 (Dec. 10, 2010).